BLOG #1 – October 27, 2026
Rhea1: From compilation to execution
By Etienne Renault, Application Sofware Manager
Introduction
European semiconductor industry has reached a new milestone! SiPearl has officially achieved the bring up phase of the Rhea1 processor, coming out directly from the European Processor Initiative (EPI).
From the Mont-Blanc project to collaborative initiatives and Center of Excellence projects (AERO, Emopass, Excellerat, Helios, HIGHER, MAX, MicroLab, ODISSEE, OpenCUBE, PLASMA-PEPSC, RISER), Rhea1 is the most complex server CPU ever developed in Europe. With it, SiPearl is paving the way for demanding HPC and AI applications.
Let’s dive into the architecture behind SiPearl’s first-generation CPU.
Key features & technical specifications
Rhea1 is designed to handle efficiently memory bound workloads while offering an impressive compute capacity. This makes it the largest CPU built in Europe. Using 61 billion transistors and TSMC N6 process node, Rhea1 features:
- Compute Engine & ISA: Rhea1 is the biggest chip based on Neoverse V1 with 80 Arm Neoverse V1 cores, each core featuring two 256-bit Scalable Vector Extension (SVE) units. It enables a vector length-agnostic programming model for various datatypes: FP64 and FP32 for HPC simulation code and BF16 and INT8 for AI. This allows Rhea1 to be versatile among the workload it can handle.
- Cache Hierarchy & Coherent Mesh (NoC): To handle cache bounded applications and ensure a fast processing of data, each core is associated with a dedicated 64KB L1 instruction/data caches and a 1MB private L2 cache. The System Level Cache (SLC) is a pool of 80MB distributed across an advanced Arm CoreLink CMN-700 Coherent Mesh Network.
- High-Speed I/O Fabric: 104 lanes of PCIe Gen5 are also available, ensuring connectivity with a wide range of devices, including accelerators, NIC, and high-speed storage arrays.
- Tiered Memory Subsystem: Rhea1 proposes an innovative memory layout designed to handle efficiently all kind of workloads
– In-package High Bandwidth Memory (4 HBM stacks) delivers the massive throughput to tackle memory-bound HPC applications like Computational Fluid Dynamics or Weather Modeling Grids.
– High-Capacity Memory (4 DDR5 channels, supporting 2 DIMMs per channel) provides expansive system memory pools for massive datasets that exceed HBM capacity. It is also the best memory to handle latency bound applications.
ISA & architecture
Rhea1 implements the ARMv8.4 instruction set, which brings specific instructions to execute advanced vector operations (like dot product, range extend single precision FMA), security (MPAM, nested virtualization) and cryptography (SHA2-512, SHA3, SM3, SM4). At the microarchitectural level, Rhea1 cores are based on Neoverse V1, which enriches the ISA enabling features that are crucial for HPC and AI, like SVE (with 256bit vectors) and bfloat16 support. For a more detailed description of the Neoverse V1 architecture, see the Arm Neoverse V1 documentation.
The backend includes functional units capable of executing scalar and vectorized code, supporting both NEON (fixed 128bit vectors) and SVE (Scalable Vector Extension). The scalable part of SVE is in the programming model: the developer doesn’t need to know the vector length for the specific architecture in advance, but rather the ISA operates on the assumption that vectors are of arbitrary power of 2 lengths, and active elements are specified via predicates. Due to this, scalable vector code can run on machines with different hardware vector lengths.
On Rhea1, SVE vectors are 256bit wide, allowing four FP64 or eight FP32 elements per vector. Rhea1 provides two 256-bit SVE vector execution units and supports FP64, FP32, BF16, and INT8 operations.
Compilers, flags & optimization impact
Neoverse V1 is well supported across the Arm compiler ecosystem, offering the developers several options from both open-source toolchains (GNU Compiler Collection, LLVM, Arm Toolchain for Linux) and vendor specific compilers (NVIDIA HPC Compilers).
To squeeze the best performance out of Rhea1, the developer needs to target both the correct instruction set and target microarchitecture. Using Clang, a typical compile command is:
In this command, the -mcpu option describes the target CPU, specifying both its instruction set (ARMv8.4-a with, among other things, the SVE and BF16 extensions enabled) and the way the instructions should be generated in order to optimise pipeline scheduling.
Compiling using the -mcpu option does not necessarily force the compiler to emit only SVE instructions for loop vectorization, the strategy can be still controlled explicitly. For instance, this command would allow the compiler to only emit NEON instructions for vectorization.
Whereas this command allows the compiler to assume a specific length of SVE registers (in this case, 256bit), which could enable more optimizations.
These two configurations provide a useful basis for comparing conventional NEON vectorization with SVE-based scalable vectorization on Rhea1.
For further reading on benchmarking and vectorization impact on Arm architecture, see our article published at the ISC High Performance 2025 conference, available as a video.
Current software ecosystem tested on Rhea1
Fully exploiting Rhea1 requires a mature software stack. Thanks to its Arm architecture, the ecosystem is fully prepared out-of-the-box.
To demonstrate this maturity, we have tested a wide variety of software. As of today, it includes open-source Compilers and Toolchains (GCC, LLVM/Clang); Numerical and System Libraries (OpenBLAS, FFTW, SLEEF, Boost, HDF5, netCDF); Runtimes (OpenMP, Kokkos); Frameworks and AI Stacks (PyTorch, TensorFlow, ONNX Runtime); and Inference Engines (vLLM, llama.cpp). In the background, various hardware Verification and Stress Suites have also been successfully executed. The table below depicts the software that has been tested, whilst the catalog you can download here provides an up-to-date list.
All these results demonstrate that Rhea1 is ready to drive European exascale computing and AI from day one.