#INTHW2312 – UPF verification flow and implementation internship (H/F)

UPF verification flow and implementation internship (H/F)


SiPearl is working on one of the most exciting and technically challenging projects in Europe right now. We are building the European high-performance low-power microprocessor for exascale supercomputers.


Power management is a critical aspect of state of the art chip design.
Our architecture integrate multiple power domains to lower the total consumption of the target super-computer.
The purpose of the internship (and follow-up collaboration) is to

  • Own the verification of all power domains using UPF verification methodology (power aware simulations)
  • Collaborate with designers and owners of the different sub-systems to identify the isolation and retention cells
  • Implement a flow to perform UPF simulation, including sleep/power-off/resume scenarios

You are or you have:

  • Master or engineering degree level
  • Verilog
  • SystemVerilog
  • RTL simulation and waveform debug
  • VHDL
  • UVM (a plus)

If you are looking for your final internship (last year of engineering school or master degree) this offer is for you !

You are motivated by working in an industrial start-up with fast growth and high visibility, having access to top silicon technology (beyond 7nm), in a competitive international environment.


Send Resume/CV and cover letter to cv@sipearl.com mentioning job reference: #INTHW2312



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