Tile Management Block UVM verification internship (H/F)
SiPearl is working on one of the most exciting and technically challenging projects in Europe right now. We are building the European high-performance low-power microprocessor for exascale supercomputers.
RESPONSIBILITIES
This proprietary IP (commonly called TMB), oversees Clock, reset, interrupts and generic IOs handling. It is a critical control block used across all sub-systems in our architecture.
The purpose of the internship will be
- To own the existing UVM verification test bench (base env. available)
- Define a test plan to improve and close the functional coverage using state of the art UVM methodology
- Own the regression status, and support RTL design and verification teams for integration of this IP at sub-system and full chip level,
- Update the test bench to follow design improvements and modification and finalize the release sign-off for tap-out
Requirements
You are or you have:
- Master or engineering degree level
- Verilog
- SystemVerilog
- RTL simulation and waveform debug
- VHDL
- UVM (a plus)
If you are looking for your final internship (last year of engineering school or master degree) this offer is for you !
You are motivated by working in an industrial start-up with fast growth and high visibility, having access to top silicon technology (beyond 7nm), in a competitive international environment.
Contact
Send Resume/CV and cover letter to cv@sipearl.com mentioning job reference: #INTHW2311
