ASIC implementation flow internship (H/F)
SiPearl is working on one of the most exciting and technically challenging projects in Europe right now. We are building the European high-performance low-power microprocessor for exascale supercomputers.
RESPONSIBILITIES
In the context of High Performance Computing (HPC), Sipearl company designs processor Rhea1, first generation of processor.
The next generation Rhea2 is major improvement for power strategy and performance (timing and area). In this context we look for an internship for implementation flow, interested in CAD tools and ASIC implementation flow.
The internship will be part of the R&D team, included in the project definition for the rhea2 processor.
Activities will include:
- Timing/Area optimisation on critical block
- Evaluate strategies for implementation with trade off between Timing and Power
- Library and memory selection
- Runtime
- Power reduction and modelling : at architecture level and/or layout level
Requirements
You are or you have:
- Motivated by the CPU design and High performance Computation in advanced technology node (Finfet)
- Willing to learn CAD tools for ASIC implementation and links at system level trade off
- Python, TCL, Perl scripting also welcome
- Master or engineering degree level
If you are looking for your final internship (last year of engineering school or master degree) this offer is for you ! You will develop CAD environment for rapid prototyping in implementation flow to support architecture and floorplan choice and trade off for rhea2 !
You are motivated by working in an industrial start-up with fast growth and high visibility, having access to top silicon technology (beyond 7nm), in a competitive international environment.
Contact
Send Resume/CV and cover letter to cv@sipearl.com mentioning job reference: #INTHW2307
