Senior logical Synthesis Engineers (M/F)
SiPearl is looking for Senior logical Synthesis engineers to be part of its growth !
Responsibilities
Reporting to the implementation team manager, you will oversee :
- Perform logical synthesis and create SDC and UPF constraints on multi-language RTL
- Work with RTL team to sort out RTL issues, suggesting solutions
- Insert Clock-Gating structures (manually and by use of tool) to improve dynamic power consumption
- Check Power-Aware structures, e.g. isolation, always-on-buffer (using UPF flow)
- Verify DfT (Scan-Chain stitching, SpyGlass DfT, Mentor tooling)
- Bring-up and pipe-clean physical aware synthesis
- Deliver timing-clean synthesis module to PnR team
- Contribute in bring-up of Synthesis Flow (using Lynx environment)
- Work with IP design teams locally or remotely
- Collaborate with ASIC service company for chip implementation in different time-zones
Location
Job opportunity in France (Maisons-Laffitte, Grenoble, Sophia-Antipolis), in Germany (Duisburg), in Spain (Barcelona).
Requirements
You are or you have:
- At least 5 years of experience of logical synthesis, constraint development and signoff
- Senior experience in using Synospys DC-NXT and Fusion-Compiler, STA tooling, especially Prime-Time
- Solid experience in RTL chip integration, including RTL design, integration and verification
- Experience using : Mentor-DfT tooling, power-aware techniques (UPF and VC LP), LYNX and/or GIT environment
- Good scripting skills, e.g. using TCL/Perl/Phyton
- Cadence tooling is a plus
PROFILE
- Problem-solving capability
- Autonomous
- Flexibility and adaptative
- Sense of initiative
- Excellent oral and writing English communication
Conditions & benefits
- Fixed salary and variable part to be defined on experience
- Restaurant tickets
- Private insurance 70% covered by SiPearl
- At least 1 day of homeoffice per week
Contact
Send Resume/CV and cover letter to cv@sipearl.com mentioning job reference: #202230
