{"id":28176,"date":"2026-10-27T18:05:44","date_gmt":"2026-10-27T17:05:44","guid":{"rendered":"https:\/\/sipearl.com\/rhea1-from-compilation-to-execution"},"modified":"2026-10-27T18:05:44","modified_gmt":"2026-10-27T17:05:44","slug":"rhea1-from-compilation-to-execution","status":"publish","type":"post","link":"https:\/\/sipearl.com\/fr\/rhea1-from-compilation-to-execution","title":{"rendered":"Rhea1: From compilation to execution"},"content":{"rendered":"<p>&nbsp;<\/p>\n<p>BLOG #1 &#8211; October 27, 2026<\/p>\n<h1 style=\"text-align: left\"><span style=\"color: #009fe3\">Rhea1: From compilation to execution<\/span><\/h1>\n<p>By Etienne Renault, Application Sofware Manager<\/p>\n<p><a href=\"https:\/\/sipearl.com\/wp-content\/uploads\/2026\/10\/SiPearl_Rhea1_From_Compilation_to_Execution_Blog_1.pdf\" target=\"_blank\" rel=\"noopener\"><strong><span style=\"color: #009fe3\">Download Blog #1 in PDF<\/span><\/strong><\/a><\/p>\n<h2><img data-recalc-dims=\"1\" loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-28112 size-full\" src=\"https:\/\/i0.wp.com\/sipearl.com\/wp-content\/uploads\/2026\/10\/SiPearl_image_Rhea1_From_Compilation_to_Execution.jpg?resize=900%2C600&#038;ssl=1\" alt=\"\" width=\"900\" height=\"600\" srcset=\"https:\/\/i0.wp.com\/sipearl.com\/wp-content\/uploads\/2026\/10\/SiPearl_image_Rhea1_From_Compilation_to_Execution.jpg?w=900&amp;ssl=1 900w, https:\/\/i0.wp.com\/sipearl.com\/wp-content\/uploads\/2026\/10\/SiPearl_image_Rhea1_From_Compilation_to_Execution.jpg?resize=300%2C200&amp;ssl=1 300w, https:\/\/i0.wp.com\/sipearl.com\/wp-content\/uploads\/2026\/10\/SiPearl_image_Rhea1_From_Compilation_to_Execution.jpg?resize=675%2C450&amp;ssl=1 675w, https:\/\/i0.wp.com\/sipearl.com\/wp-content\/uploads\/2026\/10\/SiPearl_image_Rhea1_From_Compilation_to_Execution.jpg?resize=500%2C333&amp;ssl=1 500w\" sizes=\"auto, (max-width: 900px) 100vw, 900px\" \/><\/h2>\n<h2><\/h2>\n<h2 style=\"text-align: left\">Introduction<\/h2>\n<p>European semiconductor industry has reached a new milestone! SiPearl has officially achieved the bring up phase of the Rhea1 processor, coming out directly from the European Processor Initiative (EPI).<\/p>\n<p>From the Mont-Blanc project to collaborative initiatives and Center of Excellence projects (AERO, Emopass, Excellerat, Helios, HIGHER, MAX, MicroLab, ODISSEE, OpenCUBE, PLASMA-PEPSC, RISER), Rhea1 is the most complex server CPU ever developed in Europe. With it, SiPearl is paving the way for demanding HPC and AI applications.<br \/>\nLet\u2019s dive into the architecture behind SiPearl\u2019s first-generation CPU.<\/p>\n<h2 style=\"text-align: left\">Key features &amp; technical specifications<\/h2>\n<p>Rhea1 is designed to handle efficiently memory bound workloads while offering an impressive compute capacity. This makes it the largest CPU built in Europe. Using 61 billion transistors and TSMC N6 process node, Rhea1 features:<\/p>\n<ul>\n<li>Compute Engine &amp; ISA: Rhea1 is the biggest chip based on Neoverse V1 with 80 Arm Neoverse V1 cores, each core featuring two 256-bit Scalable Vector Extension (SVE) units. It enables a vector length-agnostic programming model for various datatypes: FP64 and FP32 for HPC simulation code and BF16 and INT8 for AI. This allows Rhea1 to be versatile among the workload it can handle.<\/li>\n<li>Cache Hierarchy &amp; Coherent Mesh (NoC): To handle cache bounded applications and ensure a fast processing of data, each core is associated with a dedicated 64KB L1 instruction\/data caches and a 1MB private L2 cache. The System Level Cache (SLC) is a pool of 80MB distributed across an advanced Arm CoreLink CMN-700 Coherent Mesh Network.<\/li>\n<li>High-Speed I\/O Fabric: 104 lanes of PCIe Gen5 are also available, ensuring connectivity with a wide range of devices, including accelerators, NIC, and high-speed storage arrays.<\/li>\n<li>Tiered Memory Subsystem: Rhea1 proposes an innovative memory layout designed to handle efficiently all kind of workloads<br \/>\n&#8211; In-package High Bandwidth Memory (4 HBM stacks) delivers the massive throughput to tackle memory-bound HPC applications like Computational Fluid Dynamics or Weather Modeling Grids.<br \/>\n&#8211; High-Capacity Memory (4 DDR5 channels, supporting 2 DIMMs per channel) provides expansive system memory pools for massive datasets that exceed HBM capacity. It is also the best memory to handle latency bound applications.<\/li>\n<\/ul>\n<h2 style=\"text-align: left\">ISA &amp; architecture<\/h2>\n<p>Rhea1 implements the ARMv8.4 instruction set, which brings specific instructions to execute advanced vector operations (like dot product, range extend single precision FMA), security (MPAM, nested virtualization) and cryptography (SHA2-512, SHA3, SM3, SM4). At the microarchitectural level, Rhea1 cores are based on Neoverse V1, which enriches the ISA enabling features that are crucial for HPC and AI, like SVE (with 256bit vectors) and bfloat16 support. For a more detailed description of the Neoverse V1 architecture, see the Arm Neoverse V1 documentation.<br \/>\n<img data-recalc-dims=\"1\" loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-28137 size-full\" src=\"https:\/\/i0.wp.com\/sipearl.com\/wp-content\/uploads\/2026\/10\/ISA_and_architecture.png?resize=437%2C465&#038;ssl=1\" alt=\"Blog Rhea1: from compilation to execution\" width=\"437\" height=\"465\" srcset=\"https:\/\/i0.wp.com\/sipearl.com\/wp-content\/uploads\/2026\/10\/ISA_and_architecture.png?w=437&amp;ssl=1 437w, https:\/\/i0.wp.com\/sipearl.com\/wp-content\/uploads\/2026\/10\/ISA_and_architecture.png?resize=282%2C300&amp;ssl=1 282w, https:\/\/i0.wp.com\/sipearl.com\/wp-content\/uploads\/2026\/10\/ISA_and_architecture.png?resize=423%2C450&amp;ssl=1 423w\" sizes=\"auto, (max-width: 437px) 100vw, 437px\" \/><\/p>\n<p>The backend includes functional units capable of executing scalar and vectorized code, supporting both NEON (fixed 128bit vectors) and SVE (Scalable Vector Extension). The scalable part of SVE is in the programming model: the developer doesn\u2019t need to know the vector length for the specific architecture in advance, but rather the ISA operates on the assumption that vectors are of arbitrary power of 2 lengths, and active elements are specified via predicates. Due to this, scalable vector code can run on machines with different hardware vector lengths.<\/p>\n<p>On Rhea1, SVE vectors are 256bit wide, allowing four FP64 or eight FP32 elements per vector. Rhea1 provides two 256-bit SVE vector execution units and supports FP64, FP32, BF16, and INT8 operations.<\/p>\n<h2 style=\"text-align: left\">Compilers, flags &amp; optimization impact<\/h2>\n<p>Neoverse V1 is well supported across the Arm compiler ecosystem, offering the developers several options from both open-source toolchains (GNU Compiler Collection, LLVM, Arm Toolchain for Linux) and vendor specific compilers (NVIDIA HPC Compilers).<\/p>\n<p>To squeeze the best performance out of Rhea1, the developer needs to target both the correct instruction set and target microarchitecture. Using Clang, a typical compile command is:<\/p>\n<p><img data-recalc-dims=\"1\" loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-28143\" src=\"https:\/\/i0.wp.com\/sipearl.com\/wp-content\/uploads\/2026\/10\/Comand1_from_compilation_to_execution.png?resize=605%2C82&#038;ssl=1\" alt=\"\" width=\"605\" height=\"82\" srcset=\"https:\/\/i0.wp.com\/sipearl.com\/wp-content\/uploads\/2026\/10\/Comand1_from_compilation_to_execution.png?w=605&amp;ssl=1 605w, https:\/\/i0.wp.com\/sipearl.com\/wp-content\/uploads\/2026\/10\/Comand1_from_compilation_to_execution.png?resize=300%2C41&amp;ssl=1 300w, https:\/\/i0.wp.com\/sipearl.com\/wp-content\/uploads\/2026\/10\/Comand1_from_compilation_to_execution.png?resize=500%2C68&amp;ssl=1 500w\" sizes=\"auto, (max-width: 605px) 100vw, 605px\" \/><\/p>\n<p>In this command, the -mcpu option describes the target CPU, specifying both its instruction set (ARMv8.4-a with, among other things, the SVE and BF16 extensions enabled) and the way the instructions should be generated in order to optimise pipeline scheduling.<\/p>\n<p>Compiling using the -mcpu option does not necessarily force the compiler to emit only SVE instructions for loop vectorization, the strategy can be still controlled explicitly. For instance, this command would allow the compiler to only emit NEON instructions for vectorization.<\/p>\n<p><img data-recalc-dims=\"1\" loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-28147\" src=\"https:\/\/i0.wp.com\/sipearl.com\/wp-content\/uploads\/2026\/10\/Command2_Rhea1_from_compilation_to_execution.png?resize=605%2C129&#038;ssl=1\" alt=\"From compilation to execution\" width=\"605\" height=\"129\" srcset=\"https:\/\/i0.wp.com\/sipearl.com\/wp-content\/uploads\/2026\/10\/Command2_Rhea1_from_compilation_to_execution.png?w=605&amp;ssl=1 605w, https:\/\/i0.wp.com\/sipearl.com\/wp-content\/uploads\/2026\/10\/Command2_Rhea1_from_compilation_to_execution.png?resize=300%2C64&amp;ssl=1 300w, https:\/\/i0.wp.com\/sipearl.com\/wp-content\/uploads\/2026\/10\/Command2_Rhea1_from_compilation_to_execution.png?resize=500%2C107&amp;ssl=1 500w\" sizes=\"auto, (max-width: 605px) 100vw, 605px\" \/><\/p>\n<p>Whereas this command allows the compiler to assume a specific length of SVE registers (in this case, 256bit), which could enable more optimizations.<\/p>\n<p><img data-recalc-dims=\"1\" loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-28151\" src=\"https:\/\/i0.wp.com\/sipearl.com\/wp-content\/uploads\/2026\/10\/Command3_from-compilation_to_execution.png?resize=605%2C145&#038;ssl=1\" alt=\"\" width=\"605\" height=\"145\" srcset=\"https:\/\/i0.wp.com\/sipearl.com\/wp-content\/uploads\/2026\/10\/Command3_from-compilation_to_execution.png?w=605&amp;ssl=1 605w, https:\/\/i0.wp.com\/sipearl.com\/wp-content\/uploads\/2026\/10\/Command3_from-compilation_to_execution.png?resize=300%2C72&amp;ssl=1 300w, https:\/\/i0.wp.com\/sipearl.com\/wp-content\/uploads\/2026\/10\/Command3_from-compilation_to_execution.png?resize=500%2C120&amp;ssl=1 500w\" sizes=\"auto, (max-width: 605px) 100vw, 605px\" \/><\/p>\n<p>These two configurations provide a useful basis for comparing conventional NEON vectorization with SVE-based scalable vectorization on Rhea1.<\/p>\n<p>For further reading on benchmarking and vectorization impact on Arm architecture, see our article published at the ISC High Performance 2025 conference, available as a video.<\/p>\n<h2 style=\"text-align: left\">Current software ecosystem tested on Rhea1<\/h2>\n<p>Fully exploiting Rhea1 requires a mature software stack. Thanks to its Arm architecture, the ecosystem is fully prepared out-of-the-box.<\/p>\n<p>To demonstrate this maturity, we have tested a wide variety of software. As of today, it includes open-source <strong>Compilers and Toolchains<\/strong> (GCC, LLVM\/Clang); <strong>Numerical and System Libraries<\/strong> (OpenBLAS, FFTW, SLEEF, Boost, HDF5, netCDF); <strong>Runtimes<\/strong> (OpenMP, Kokkos); <strong>Frameworks and AI Stacks<\/strong> (PyTorch, TensorFlow, ONNX Runtime); and <strong>Inference Engines<\/strong> (vLLM, llama.cpp). In the background, various hardware <strong>Verification and Stress Suites<\/strong> have also been successfully executed. The table below depicts the software that has been tested, whilst the catalog you can <a href=\"https:\/\/sipearl.com\/wp-content\/uploads\/2026\/10\/SiPearl_Rhea1_From_Compilation_to_Execution_Table_Blog_1.pdf\" target=\"_blank\" rel=\"noopener\"><strong><span style=\"color: #009fe3\">download here<\/span><\/strong><\/a> provides an up-to-date list.<\/p>\n<p>All these results demonstrate that Rhea1 is ready to drive European exascale computing and AI from day one.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>&nbsp; BLOG #1 &#8211; October 27, 2026 Rhea1: From compilation to execution By Etienne Renault, Application Sofware Manager Download Blog #1 in PDF Introduction European semiconductor industry has reached a new milestone! SiPearl has officially achieved the bring up phase of the Rhea1 processor, coming out directly from the European Processor Initiative (EPI). From the&#8230;<\/p>\n","protected":false},"author":1,"featured_media":28113,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_jetpack_newsletter_access":"","_jetpack_dont_email_post_to_subs":false,"_jetpack_newsletter_tier_id":0,"_jetpack_memberships_contains_paywalled_content":false,"_jetpack_feature_clip_id":0,"_jetpack_memberships_contains_paid_content":false,"footnotes":"","jetpack_post_was_ever_published":false},"categories":[1],"tags":[146],"class_list":["post-28176","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-non-classifiee","tag-blog"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v28.8 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Rhea1: From compilation to execution - SiPearl<\/title>\n<meta name=\"description\" content=\"In Blog #1 entitled &quot;Rhea1: From compilation to execution&quot;, SiPearl dives into the architecture behind SiPearl&#039;s first-generation CPU.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/sipearl.com\/fr\/rhea1-from-compilation-to-execution\" \/>\n<meta property=\"og:locale\" content=\"fr_FR\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Rhea1: From compilation to execution - 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SiPearl\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/sipearl.com\\\/fr#website\"},\"primaryImageOfPage\":{\"@id\":\"https:\\\/\\\/sipearl.com\\\/fr\\\/rhea1-from-compilation-to-execution#primaryimage\"},\"image\":{\"@id\":\"https:\\\/\\\/sipearl.com\\\/fr\\\/rhea1-from-compilation-to-execution#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/i0.wp.com\\\/sipearl.com\\\/wp-content\\\/uploads\\\/2026\\\/10\\\/SiPearl_image_Rhea1_From_Compilation_to_Execution.jpg?fit=900%2C600&ssl=1\",\"datePublished\":\"2026-10-27T17:05:44+00:00\",\"description\":\"In Blog #1 entitled \\\"Rhea1: From compilation to execution\\\", SiPearl dives into the architecture behind SiPearl's first-generation CPU.\",\"breadcrumb\":{\"@id\":\"https:\\\/\\\/sipearl.com\\\/fr\\\/rhea1-from-compilation-to-execution#breadcrumb\"},\"inLanguage\":\"fr-FR\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\\\/\\\/sipearl.com\\\/fr\\\/rhea1-from-compilation-to-execution\"]}]},{\"@type\":\"ImageObject\",\"inLanguage\":\"fr-FR\",\"@id\":\"https:\\\/\\\/sipearl.com\\\/fr\\\/rhea1-from-compilation-to-execution#primaryimage\",\"url\":\"https:\\\/\\\/i0.wp.com\\\/sipearl.com\\\/wp-content\\\/uploads\\\/2026\\\/10\\\/SiPearl_image_Rhea1_From_Compilation_to_Execution.jpg?fit=900%2C600&ssl=1\",\"contentUrl\":\"https:\\\/\\\/i0.wp.com\\\/sipearl.com\\\/wp-content\\\/uploads\\\/2026\\\/10\\\/SiPearl_image_Rhea1_From_Compilation_to_Execution.jpg?fit=900%2C600&ssl=1\",\"width\":900,\"height\":600},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\\\/\\\/sipearl.com\\\/fr\\\/rhea1-from-compilation-to-execution#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Accueil\",\"item\":\"https:\\\/\\\/sipearl.com\\\/fr\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"Rhea1: From compilation to execution\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\\\/\\\/sipearl.com\\\/fr#website\",\"url\":\"https:\\\/\\\/sipearl.com\\\/fr\",\"name\":\"SiPearl\",\"description\":\"le microprocesseur europ\u00e9en\",\"publisher\":{\"@id\":\"https:\\\/\\\/sipearl.com\\\/fr#organization\"},\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\\\/\\\/sipearl.com\\\/fr?s={search_term_string}\"},\"query-input\":{\"@type\":\"PropertyValueSpecification\",\"valueRequired\":true,\"valueName\":\"search_term_string\"}}],\"inLanguage\":\"fr-FR\"},{\"@type\":\"Organization\",\"@id\":\"https:\\\/\\\/sipearl.com\\\/fr#organization\",\"name\":\"SiPearl\",\"url\":\"https:\\\/\\\/sipearl.com\\\/fr\",\"logo\":{\"@type\":\"ImageObject\",\"inLanguage\":\"fr-FR\",\"@id\":\"https:\\\/\\\/sipearl.com\\\/fr#\\\/schema\\\/logo\\\/image\\\/\",\"url\":\"https:\\\/\\\/sipearl.com\\\/wp-content\\\/uploads\\\/2021\\\/08\\\/logo_SIPEARL.png\",\"contentUrl\":\"https:\\\/\\\/sipearl.com\\\/wp-content\\\/uploads\\\/2021\\\/08\\\/logo_SIPEARL.png\",\"width\":1146,\"height\":396,\"caption\":\"SiPearl\"},\"image\":{\"@id\":\"https:\\\/\\\/sipearl.com\\\/fr#\\\/schema\\\/logo\\\/image\\\/\"},\"sameAs\":[\"https:\\\/\\\/x.com\\\/SIPEARL_SAS\",\"https:\\\/\\\/www.linkedin.com\\\/company\\\/sipearl\\\/\"]},{\"@type\":\"Person\",\"@id\":\"https:\\\/\\\/sipearl.com\\\/fr#\\\/schema\\\/person\\\/79862e28cefefda0657f78f4376e1302\",\"name\":\"Singer75016\",\"image\":{\"@type\":\"ImageObject\",\"inLanguage\":\"fr-FR\",\"@id\":\"https:\\\/\\\/secure.gravatar.com\\\/avatar\\\/aa09218079c8c02aa7353b7d21f906acebd5d2171b2f00d1bef45a4d009fffdb?s=96&d=mm&r=g\",\"url\":\"https:\\\/\\\/secure.gravatar.com\\\/avatar\\\/aa09218079c8c02aa7353b7d21f906acebd5d2171b2f00d1bef45a4d009fffdb?s=96&d=mm&r=g\",\"contentUrl\":\"https:\\\/\\\/secure.gravatar.com\\\/avatar\\\/aa09218079c8c02aa7353b7d21f906acebd5d2171b2f00d1bef45a4d009fffdb?s=96&d=mm&r=g\",\"caption\":\"Singer75016\"},\"sameAs\":[\"https:\\\/\\\/sipearl.com\"],\"url\":\"https:\\\/\\\/sipearl.com\\\/fr\\\/author\\\/singer75016\"}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"Rhea1: From compilation to execution - SiPearl","description":"In Blog #1 entitled \"Rhea1: From compilation to execution\", SiPearl dives into the architecture behind SiPearl's first-generation CPU.","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/sipearl.com\/fr\/rhea1-from-compilation-to-execution","og_locale":"fr_FR","og_type":"article","og_title":"Rhea1: From compilation to execution - SiPearl","og_description":"In Blog #1 entitled \"Rhea1: From compilation to execution\", SiPearl dives into the architecture behind SiPearl's first-generation CPU.","og_url":"https:\/\/sipearl.com\/fr\/rhea1-from-compilation-to-execution","og_site_name":"SiPearl","article_published_time":"2026-10-27T17:05:44+00:00","og_image":[{"width":900,"height":600,"url":"https:\/\/sipearl.com\/wp-content\/uploads\/2026\/10\/SiPearl_image_Rhea1_From_Compilation_to_Execution.jpg","type":"image\/jpeg"}],"author":"Singer75016","twitter_card":"summary_large_image","twitter_creator":"@SIPEARL_SAS","twitter_site":"@SIPEARL_SAS","twitter_misc":{"\u00c9crit par":"Singer75016","Dur\u00e9e de lecture estim\u00e9e":"5 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Article","@id":"https:\/\/sipearl.com\/fr\/rhea1-from-compilation-to-execution#article","isPartOf":{"@id":"https:\/\/sipearl.com\/fr\/rhea1-from-compilation-to-execution"},"author":{"name":"Singer75016","@id":"https:\/\/sipearl.com\/fr#\/schema\/person\/79862e28cefefda0657f78f4376e1302"},"headline":"Rhea1: From compilation to execution","datePublished":"2026-10-27T17:05:44+00:00","mainEntityOfPage":{"@id":"https:\/\/sipearl.com\/fr\/rhea1-from-compilation-to-execution"},"wordCount":917,"publisher":{"@id":"https:\/\/sipearl.com\/fr#organization"},"image":{"@id":"https:\/\/sipearl.com\/fr\/rhea1-from-compilation-to-execution#primaryimage"},"thumbnailUrl":"https:\/\/i0.wp.com\/sipearl.com\/wp-content\/uploads\/2026\/10\/SiPearl_image_Rhea1_From_Compilation_to_Execution.jpg?fit=900%2C600&ssl=1","keywords":["blog"],"articleSection":["Non classifi\u00e9(e)"],"inLanguage":"fr-FR"},{"@type":"WebPage","@id":"https:\/\/sipearl.com\/fr\/rhea1-from-compilation-to-execution","url":"https:\/\/sipearl.com\/fr\/rhea1-from-compilation-to-execution","name":"Rhea1: From compilation to execution - SiPearl","isPartOf":{"@id":"https:\/\/sipearl.com\/fr#website"},"primaryImageOfPage":{"@id":"https:\/\/sipearl.com\/fr\/rhea1-from-compilation-to-execution#primaryimage"},"image":{"@id":"https:\/\/sipearl.com\/fr\/rhea1-from-compilation-to-execution#primaryimage"},"thumbnailUrl":"https:\/\/i0.wp.com\/sipearl.com\/wp-content\/uploads\/2026\/10\/SiPearl_image_Rhea1_From_Compilation_to_Execution.jpg?fit=900%2C600&ssl=1","datePublished":"2026-10-27T17:05:44+00:00","description":"In Blog #1 entitled \"Rhea1: From compilation to execution\", SiPearl dives into the architecture behind SiPearl's first-generation CPU.","breadcrumb":{"@id":"https:\/\/sipearl.com\/fr\/rhea1-from-compilation-to-execution#breadcrumb"},"inLanguage":"fr-FR","potentialAction":[{"@type":"ReadAction","target":["https:\/\/sipearl.com\/fr\/rhea1-from-compilation-to-execution"]}]},{"@type":"ImageObject","inLanguage":"fr-FR","@id":"https:\/\/sipearl.com\/fr\/rhea1-from-compilation-to-execution#primaryimage","url":"https:\/\/i0.wp.com\/sipearl.com\/wp-content\/uploads\/2026\/10\/SiPearl_image_Rhea1_From_Compilation_to_Execution.jpg?fit=900%2C600&ssl=1","contentUrl":"https:\/\/i0.wp.com\/sipearl.com\/wp-content\/uploads\/2026\/10\/SiPearl_image_Rhea1_From_Compilation_to_Execution.jpg?fit=900%2C600&ssl=1","width":900,"height":600},{"@type":"BreadcrumbList","@id":"https:\/\/sipearl.com\/fr\/rhea1-from-compilation-to-execution#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Accueil","item":"https:\/\/sipearl.com\/fr"},{"@type":"ListItem","position":2,"name":"Rhea1: From compilation to execution"}]},{"@type":"WebSite","@id":"https:\/\/sipearl.com\/fr#website","url":"https:\/\/sipearl.com\/fr","name":"SiPearl","description":"le microprocesseur europ\u00e9en","publisher":{"@id":"https:\/\/sipearl.com\/fr#organization"},"potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/sipearl.com\/fr?s={search_term_string}"},"query-input":{"@type":"PropertyValueSpecification","valueRequired":true,"valueName":"search_term_string"}}],"inLanguage":"fr-FR"},{"@type":"Organization","@id":"https:\/\/sipearl.com\/fr#organization","name":"SiPearl","url":"https:\/\/sipearl.com\/fr","logo":{"@type":"ImageObject","inLanguage":"fr-FR","@id":"https:\/\/sipearl.com\/fr#\/schema\/logo\/image\/","url":"https:\/\/sipearl.com\/wp-content\/uploads\/2021\/08\/logo_SIPEARL.png","contentUrl":"https:\/\/sipearl.com\/wp-content\/uploads\/2021\/08\/logo_SIPEARL.png","width":1146,"height":396,"caption":"SiPearl"},"image":{"@id":"https:\/\/sipearl.com\/fr#\/schema\/logo\/image\/"},"sameAs":["https:\/\/x.com\/SIPEARL_SAS","https:\/\/www.linkedin.com\/company\/sipearl\/"]},{"@type":"Person","@id":"https:\/\/sipearl.com\/fr#\/schema\/person\/79862e28cefefda0657f78f4376e1302","name":"Singer75016","image":{"@type":"ImageObject","inLanguage":"fr-FR","@id":"https:\/\/secure.gravatar.com\/avatar\/aa09218079c8c02aa7353b7d21f906acebd5d2171b2f00d1bef45a4d009fffdb?s=96&d=mm&r=g","url":"https:\/\/secure.gravatar.com\/avatar\/aa09218079c8c02aa7353b7d21f906acebd5d2171b2f00d1bef45a4d009fffdb?s=96&d=mm&r=g","contentUrl":"https:\/\/secure.gravatar.com\/avatar\/aa09218079c8c02aa7353b7d21f906acebd5d2171b2f00d1bef45a4d009fffdb?s=96&d=mm&r=g","caption":"Singer75016"},"sameAs":["https:\/\/sipearl.com"],"url":"https:\/\/sipearl.com\/fr\/author\/singer75016"}]}},"jetpack_sharing_enabled":true,"jetpack_featured_media_url":"https:\/\/i0.wp.com\/sipearl.com\/wp-content\/uploads\/2026\/10\/SiPearl_image_Rhea1_From_Compilation_to_Execution.jpg?fit=900%2C600&ssl=1","_links":{"self":[{"href":"https:\/\/sipearl.com\/fr\/wp-json\/wp\/v2\/posts\/28176","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/sipearl.com\/fr\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/sipearl.com\/fr\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/sipearl.com\/fr\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/sipearl.com\/fr\/wp-json\/wp\/v2\/comments?post=28176"}],"version-history":[{"count":0,"href":"https:\/\/sipearl.com\/fr\/wp-json\/wp\/v2\/posts\/28176\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/sipearl.com\/fr\/wp-json\/wp\/v2\/media\/28113"}],"wp:attachment":[{"href":"https:\/\/sipearl.com\/fr\/wp-json\/wp\/v2\/media?parent=28176"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/sipearl.com\/fr\/wp-json\/wp\/v2\/categories?post=28176"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/sipearl.com\/fr\/wp-json\/wp\/v2\/tags?post=28176"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}