In collaboration with its industrial and academic partners and research institutes, SiPearl takes part in several iconic projects contributing to the renewal of high performance and low power microprocessor technologies in Europe. Among them: Mont-Blanc 2020, European Processor Initiative (EPI) Phase 1 and Phase 2, Emopass.
Mont-Blanc 2020, a pilot for the European microprocessor specifications
The Mont-Blanc 2020 project ended on 31 March 2021. It fulfilled its objective of delivering a pilot for some of the specifications of the ARM Neoverse V1 based European microprocessor and some of its IP blocks dedicated to HPC.
It was used by the European Processor Initiative consortium to define the roadmap for Rhea, the microprocessor developed by SiPearl.
European Processor Initiative Phase 1,
the European microprocessor roadmap
Launched in December 2018, the project of the European Processor Initiative (EPI) consortium aims to bring to market a high performance, low-power microprocessor and ensure that the key competences for high-end microprocessor design remain in Europe. The European Union’s Horizon 2020 program funds this project with a special Framework Partnership Agreement.
The 1st phase of the project was completed in November 2021, delivering cutting-edge technologies for European sovereignty on time and within a limited budget, despite the constraints of the COVID-19 pandemic. It includes the definition of the architectural specifications of Rhea, the 1st generation European microprocessor implementation and its future derivates. With 29 RISC-V cores, the Arm Neoverse V1 architecture used by SiPearl to design Rhea will offer an effective, scalable and customisable solution for HPC applications.
The successful completion of this phase paves the way for the second phase of the project, which had kicked off in January 2022.
The EPI consortium includes experts in all the relevant areas: the HPC research community, major supercomputing centres, the computer system, automotive, and silicon industry, as well as the potential scientific and industrial users. SiPearl is the private company that emerged from the consortium and its 28th member.
European Processor Initiative Phase 2,
a more powerful and efficient microprocessor
Launched by the Euro-HPC Joint Undertaking in January 2022, the European Processor Initiative Phase 2 aims to:
strengthen the competitiveness and leadership of European industry and science;
develop European microprocessor technology with drastically better performance and power ratios;
tackle important segments of broader and/or emerging HPC and big-data markets.
In particular, it will move forward with the development of the European microprocessor targeting future European exascale supercomputers by applying technological enhancements to the baseline of Rhea. With its partners, SiPearl will increase the number of cores and memory bandwidth, and also add chip acceleration and custom IP blocks.
In parallel, the partners focus on the development of an open common platform standard aiming to efficiently interface microprocessors and accelerators in-package, implementing cache coherency, and validating the toolchains and runtime between microprocessors and accelerators.
Emopass, to optimize the performance and efficiency of the European microprocessor
The Emopass project intends to build the basis of a software ecosystem that will optimise the performance and energy consumption of Rhea for HPC applications such as artificial intelligence, meteorological, climatic, seismic, medical and pharmaceutical modelling.
SiPearl is working hand in hand with Atos and the Laboratory of Parallelism and Distributed Algorithm Networks (LI-PaRAD) of the University of Versailles Saint-Quentin-en-Yvelines on this project. The Emopass project is supported by the Ile-de-France Region and Bpifrance.
Our partners
They support us
Riser: First all-European Risc-V cloud server infrastructure
Riser will develop the first all-European Risc-V cloud server infrastructure, significantly enhancing Europe’s open strategic autonomy. Riser will leverage and validate open hardware high-speed interfaces combined with a fully-featured operating system environment and runtime system, enabling the integration of low-power components, including Risc-V processor chips from the EPI and Eupilot projects, in a novel energy-efficient cloud architecture.
With a 36 months duration (until December 31, 2025), Riser is supported by the European Union under the Horizon Europe 2027 programme.
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