RTL Design EngineerS IP level (M/F)
RESPONSIBILITIES
SiPearl is looking for RTL Design Engineers IP level to consolidate our growth !
Reporting to the HW team manager, you will oversee:
- Read and analysize the system requirement and architecture requirement documents
- Work with architecture team to mature the design specifications for further implementation
- Coding in HDL to implement desired functions based on design specifications
- Design or integrate the testbench for design verification
- Generate design report to detail functions and behavior
- Create application guide for h/w and s/w integration
- Work with integration teams to participate in design integration
- Help model teams to build model of the design and get it integrated
- Work with verification teams to verify the design with module-test or system-level-test
- Collaborate with firmware teams support developing firmware and drivers
- Packaging the design into IP for future reuse
- Guide and review the junior in the team as the menter
Job opportunity in France (Massy, Maisons-Laffitte, Grenoble, Sophia-Antipolis), in Germany (Duisburg), in Spain (Barcelona).
REQUIREMENTS
You are or you have:
- At least 2 years of digital HDL design or integration
- At least 1 year of digital design verification using SystemVerilog
- Senior experience of coverage-based verification and use of verification IP’s
- Experience of using verification management tools & external verification resources
- (Preferred) Team building skills
- (Optional) Working with AMBA and Arm IP designs
PROFILE
- Someone adaptable
- Autonomous
- Excellent oral and writing English communication
CONDITIONS & BENEFITS
- Fixed salary and variable part to be defined on experience
- Restaurant tickets
- Private insurance 70% covered by SiPearl
- At least 1 day of homeoffice per week
CONTACT
Send Resume/CV and cover letter to cv@sipearl.com mentioning job reference: #202220
