#202206 – Functional verification Engineers subsystem level (M/F)

Functional verification engineers subsystem level (M/F)



SiPearl is looking for Functional verification engineers subsystem level 

Reporting to the design team manager, you will oversee:

  • Read and analysize the system requirement and architecture requirement documents
  • Plan for functional verification activities
  • Managing the verification activities for the chips
  • Project milestones and deliverables planning with respect to functional verification within SiPearl and with external partners
  • Project reporting
  • Organize work and deliverables between skills, internal and external teams
  • Technical team steering and guiding, removing roadblocks

Job opportunity in Germany (Duisburg), in France (Paris area, Maisons-Laffitte, Grenoble, Sophia-Antipolis), in Spain (Barcelona).


You are or you have:

  • At least 4 years of digital HDL design or integration
  • At least 2 years of digital design verification using SystemVerilog
  • Senior experience of coverage-based verification and use of verification IP’s.
  • Experience of using verification management tools.
  • Experience of using external verification resources.
  • (Preferred) Experience of team building
  • (Optional) Experience of AMBA and Arm IP designs
  • Someone adaptable
  • Autonomous
  • Excellent oral and writing English communication.
Conditions & benefits

Fixe and variable part to be defined on experience.


Send Resume/CV and cover letter to cv@sipearl.com mentioning job reference: #202206




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