Junior RTL Design engineerS SoC Level (M/F)
Responsibilities
SiPearl is looking for Junior RTL Design engineers SoC Level
Reporting to the design team manager, you will oversee:
- Read and analysize the system requirement and architecture requirement documents
- Identify the gap between available IPs and the system requirements; build glue logics or generate the design spec for the the glue logics
- Work with other team members in the integration; integrate the design, generate the timing constraints and synthesize the design
- Participate in DFT activities with the DFT service from the product engineering team internally or from the ASIC service
- Work with IP design teams locally or remotely
- Work with verification teams remotely
- Work with ASIC service company for chip implementation, in Europe or in different timezones”
Location
Job opportunity in Germany (Duisburg), in France (Maisons-Laffitte, Grenoble).
Requirements
You are or you have:
- At least 4 years of digital HDL functional design or integration
- At least 2 years experiences specifically in integrating digital designs for complex chip or SoC, including integration, synthesis, STA and DFT related activities.
- Experience of using tools and script language for automated integration
- Experience of using Synopsys tools (Spyglass, DC, Primetime)
- (Preferred) Experience of using Mentor tools (Questa-sim, LEC)
- (Preferred) Experience of using AMBA and Arm IPs
- (Optionally) Experience of script design for automation
PROFILE
- Someone adaptable
- Autonomous
- Excellent oral and writing English communication
Conditions & benefits
Fixe and variable part to be defined on experience.
Contact
Send Resume/CV and cover letter to cv@sipearl.com mentioning job reference: #202201
