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ASIC Design Verification Internship

  • 1 déc. 2021 - Ref: #INTHW02
SiPearl’s Rhea processor is designed for High-Performance Computing (HPC) supercomputers.
Nowadays, the memory subsystem has become a bottleneck for many HPC applications. the memory subsystem has become a bottleneck for many HPC applications. For this reason, Rhea features two types of memory elements, to ensure both high bandwidth and high capacity.

The memory subsystem is crucial and a particular care must be given to the functional verification of its blocs. We are seeking elite ASIC verification interns to take on the task of verifying the design and implementation of the European processor.

Description du poste :
This position will offer to you a unique opportunity to have a real impact in a dynamic team and technology disruptive company. Your mission as intern will consist of:

Taking ownership of the UVM functional verification environments provided by a subcontractor for the two subsystems

Establishing verification plans corresponding to the available environments (UVM and hybrid C/C++/SystemC) and aligned with the requirements of the project

Improving the verification environments by modifying and adding tests to cover the verification plan, optimize performance, improve reporting, and facilitate debugging

Ensuring excellent coverage of the functionality of the blocs in the many use cases relevant to high-performance computing

Integrating a subset of the verification tests into a continuous integration workflow, including hardware acceleration targets on Mentor Veloce emulator


Job based in Paris Area : Maisons-Laffitte (78)


Vous êtes :
Engineering school or university


At least 2 of:

verilog, system verilog, pert, python, gitlab, UVM, formal, knowledge in functional verification, emulation, knowledge in physical implementation, CPU architecture, C++


Conditions et Avantages :
Conventional bonus

Contact :
Envoyer CV et lettre de candidature à cv@sipearl.com
en mentionnant la référence de l'annonce : #INTHW02
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